1. Field of the Invention
The present invention relates to a synchronous rectification circuit with dead time regulation and, in particular, to a synchronous rectification circuit with dead time regulation using forward power supply.
2. Description of the Related Art
In order to minimize the size of a transformer in a known DC power supply apparatus, such as an AC to DC switching power supply, high frequency pulse width modulation (PWM) is usually used for control of a DC output voltage. As shown in FIG. 1, a schematic circuit diagram of a forward power supply apparatus, which is separated by a transformer T1 into a primary front-end circuit 101 and a secondary back-end circuit 102, is shown. The back-end circuit 102 is composed of a first switch Q1, a second switch Q2, an inductor L and a capacitor C. Two terminals V1 and V2 on the secondary side of the transformer T1 are connected to gate terminals G1 and G2 of the first switch Q1 and the second switch Q2, respectively, for controlling the ON/OFF of the first switch Q1 and the second switch Q2, which in turn operate in combination with the energy-storage inductor L and the filtering capacitor C to produce a stable output DC voltage Vo.
With reference to FIG. 2, waveforms at various nodes in the circuit of the prior art forward power supply apparatus in FIG. 1 are schematically shown. In the drawing, the horizontal axis represents time t while the vertical axis represents voltage v. During the time interval t0–t1, the terminal V1 on the secondary side of the transformer T1 is HIGH and the terminal V2 is LOW, so the gate terminal G1 of the first switch Q1 connected to the terminal V1 is HIGH and the gate terminal G2 of the second switch Q2 connected to the terminal V2 is LOW. At this time, the first switch Q1 conducts and the second switch Q2 is cutoff.
During the time interval t1–t2, the terminal V1 becomes LOW and the terminal V2 becomes HIGH, so the gate terminal G1 of the first switch Q1 connected to the terminal V1 is LOW and the gate terminal G2 of the second switch Q2 connected to the terminal V2 is HIGH. At this time, the first switch Q1 is cutoff and the second switch Q2 conducts.
During the time interval t2–t3, the terminal V1 remains LOW and thus the first switch Q1 is still cutoff. However, at this time, the voltage at the terminal V2, which is connected to the gate terminal G2 of the second switch Q2, drops below a cutoff voltage VP allowing the second switch Q2 to conduct, driving the second switch Q2 into cutoff in advance. Now the circuit enters into the dead time.
During the time interval t3–t4, the terminal V1 remains LOW and thus the first switch Q1 is still cutoff. Meanwhile, the terminal V2 drops to LOW. Consequently, the second switch Q2 remains cutoff. At this time, the circuit is also in the dead time. In the above description, the first switch Q1 and the second switch Q2 are both MOSFETs.
In summary, the dead time in the circuit of the prior art forward power supply apparatus is t2–t4. Such a dead time varies with a conducting cycle at the terminal V1 on the secondary side of the transformer T1 and, more specifically, the shorter the conducting cycle at the terminal V1, the longer the dead time. Further, a shorter conducting cycle at the terminal V2 on the secondary side of the transformer T1 adversely affects the efficiency of the circuit.
Moreover, although the prior art forward power supply apparatus has a simple circuit structure, the output voltage level is very limited, usually to an output voltage of under 3.3V. The reason for this is that the voltage of the transformer is at least approximately 2.5–4 times the output voltage and the voltage on the secondary side of the transformer exceeds a withstand voltage of a gate-source voltage of a MOSFET switch in an application having an output voltage of 3.3V or more.
Furthermore, in the circuit of the prior art forward power supply apparatus, the second switch Q2 and the first switch Q1 will both conduct for a short period at the time when the conducting cycle of the second switch Q2 is about to terminate, resulting in a switching loss. This effect is especially significant when the output voltage is high.